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INTEGRATED CIRCUITS
DATA SHEET
SAA6588 RDS/RBDS pre-processor
Product specification Supersedes data of 1997 Sep 01 File under Integrated Circuits, IC01 2002 Jan 14
Philips Semiconductors
Product specification
RDS/RBDS pre-processor
FEATURES * Integrated switched capacitor filters * Demodulation of the European Radio Data System (RDS) or the USA Radio Broadcast Data System (RBDS) signal * RDS and RBDS block detection * Error detection and correction * Fast block synchronization * Synchronization control (flywheel) * Mode control for RDS/RBDS processing * Different RDS/RBDS block information output modes (e.g. A-block output mode) * Fast I2C-bus interface * Multi-path detector * Signal quality detector with sensitivity adjustment * Pause detector with pause level and time adjustment * Alternatively oscillator frequency: n x 4.332 MHz (n = 1 to 4) * UART compatible with 17.328 MHz (n = 4) * CMOS device * Single supply voltage * Extended temperature range (-40 to +85 C). GENERAL DESCRIPTION Today most FM radio stations in Europe and meanwhile also many FM/AM radio broadcasting stations in the USA transmit the inaudible European RDS (Radio Data System) or the USA RBDS (Radio Broadcast Data System) informations respectively. Likewise nowadays receivers, most car radios and also some home and portable radios on the market include at least some of the RDS features. The RDS/RBDS system offers a large range of applications by its many functions to be implemented. For car radios the most important are: * Program Service (PS) name * Traffic Program (TP) identification * Traffic Announcement (TA) signal * Alternative Frequency (AF) list * Program Identification (PI) * Enhanced Other Networks (EON) information.
SAA6588
The RDS/RBDS pre-processor is a CMOS device that integrates all RDS/RBDS relevant functions in one chip. The IC contains filtering and demodulation of the RDS/RBDS signal, symbol decoding, block synchronization, error detection, error correction and additional detectors for multi-path, signal quality and audio signal pauses. The pre-processed RDS/RBDS information is available via the I2C-bus. The RDS/RBDS pre-processor replaces a number of ICs and peripheral components used nowadays in car radio concepts with RDS or RBDS features. The integration of the relevant RDS/RBDS data processing functions provides, in an economic manner, high performance of RDS/RBDS processing and reduces the real-time requirements for the main radio microcontroller considerably. In addition it simplifies the development of the RDS specific software for the main controller of the radio set. Compared with standard radio systems, RDS/RBDS controlled radio systems additionally require an RDS/RBDS demodulator with a 57 kHz band-pass filter, information about the current reception situation (reception quality, multi-path disturbance etc.), and additional microcontroller power for RDS/RBDS data processing, decoding and radio control. The new RDS/RBDS pre-processor includes all these specific functions and meets all requirements of a high end RDS/RBDS radio. Moreover the timing requirements of the set controller, regarding RDS/RBDS data processing are reduced due to the integration of decoder functions, so that the development of radio control software can be concentrated specifically on radio set features.
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Philips Semiconductors
Product specification
RDS/RBDS pre-processor
QUICK REFERENCE DATA SYMBOL VDDA VDDD IDD(tot) Vi(MPX) GSQ CRGSQ tPON(min) fi(xtal) PARAMETER analog supply voltage digital supply voltage total supply current RDS input sensitivity at pin MPX step size for signal quality input gain control range for signal quality input gain minimum time for pause crystal input frequency adjustable in 4 steps n=1 n=2 n=3 n=4 ORDERING INFORMATION TYPE NUMBER SAA6588 SAA6588T PACKAGE NAME DIP20 SO20 DESCRIPTION plastic dual in-line package; 20 leads (300 mil) plastic small outline package; 20 leads; body width 7.5 mm CONDITIONS MIN. 4.5 4.5 - 1 - - 20.2 - - - - TYP. 5.0 5.0 14.0 - 0.6 18.6 - 4.332 8.664 12.996 17.328
SAA6588
MAX. 5.5 5.5 - - - - 161.7 - - - -
UNIT V V mA mV dB dB ms MHz MHz MHz MHz
VERSION SOT146-1 SOT163-1
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560 pF C10 SCOUT 18 57 kHz 8th ORDER BAND-PASS CIN 19 VDDD 7 multiplex C1 input C2 audio inputs C3 330 pF 0.47 F 0.47 F R2 10 R3 k 11 PSWN 10 k AFIN 13 PAUSE DETECTOR 2 MPTH MPX 16 CLOCKED COMPARATOR
BLOCK DIAGRAM
Philips Semiconductors
handbook, full pagewidth
RDS/RBDS pre-processor
+5 V
C9 100 nF
RDS/RDBS DEMODULATOR
RDS/RDBS DECODER
8 DAVN
data available pause output multi-path output
SAA6588
MULTI-PATH DETECTOR SIGNAL QUALITY DETECTOR 4 INTERFACE REGISTER
5 level input +5 V C8 100 nF C11 2.2 nF VDDA 14 POWER SUPPLY AND RESET 15 VSSA 17 Vref C7 2.2 F TEST CONTROL 3 TCON C6 100 nF 1 MRO R4 470 k C4 47 pF OSCILLATOR AND CLOCK 5 OSCI Q1 n x 4.332 MHz n = 1 to 4 4 OSCO R1 1 k
MGK535
4
4 LVIN 20
9 SDA I2C-BUS SLAVE TRANSCEIVER 6 VSSD 12 MAD 10 SCL I2C-BUS
C5 82 pF
Product specification
SAA6588
Fig.1 Block diagram.
Philips Semiconductors
Product specification
RDS/RBDS pre-processor
PINNING SYMBOL MRO MPTH TCON OSCO OSCI VSSD VDDD DAVN SDA SCL PIN 1 2 3 4 5 6 7 8 9 10 DESCRIPTION multi-path rectifier output multi-path detector output test control input pin oscillator output oscillator input digital ground (0 V) digital supply voltage (5 V) data available output (active LOW) I2C-bus serial data I/O I2C-bus serial clock input
SAA6588
SYMBOL PSWN MAD AFIN VDDA VSSA MPX Vref SCOUT CIN LVIN
PIN 11 12 13 14 15 16 17 18 19 20
DESCRIPTION pause switch output (active LOW) slave address (LSB) input audio signal input analog supply voltage (5 V) analog ground (0 V) multiplex input signal reference voltage output band-pass filter output comparator input level input
handbook, halfpage
MRO 1
handbook, halfpage
20 LVIN 19 CIN 18 SCOUT 17 Vref 16 MPX
MRO 1 MPTH 2 TCON 3 OSCO 4 OSCI 5
20 LVIN 19 CIN 18 SCOUT 17 Vref 16 MPX
MPTH 2 TCON 3 OSCO 4 OSCI 5
SAA6588T
VSSD 6 VDDD 7 DAVN 8 SDA 9 SCL 10
MGK534
SAA6588
VSSD 6 VDDD 7 DAVN 8 SDA 9 SCL 10
MGK533
15 VSSA 14 VDDA 13 AFIN 12 MAD 11 PSWN
15 VSSA 14 VDDA 13 AFIN 12 MAD 11 PSWN
Fig.2 Pin configuration (DIP20).
Fig.3 Pin configuration (SO20).
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Philips Semiconductors
Product specification
RDS/RBDS pre-processor
FUNCTIONAL DESCRIPTION General The following functions are performed by the SAA6588: * Selection of the RDS/RBDS signal from the MPX input signal * 57 kHz carrier regeneration * Demodulation of the RDS/RBDS signal * Symbol decoding * RDS/RBDS block detection * Error detection and correction of transmission errors * Fast block synchronization and synchronization control * Detection of multi-path distortion and audio signal pauses * Determination of the signal quality * Mode control of processing and RDS/RBDS data output via I2C-bus interface * Sensing of pause and multi-path, information via extra output pins. The block diagram of the RDS/RBDS pre-processor is shown in Fig.1. For the application of the device only a few external components are required. The pre-processors functional blocks are described in the following sections. RDS/RBDS signal demodulation BAND-PASS FILTER The band-pass filter has a centre frequency of 57 kHz. It selects the RDS/RBDS sub-band from the multiplex signal MPX and suppresses the audio signal components. The filter block contains an analog anti-aliasing filter at the input followed by an 8th order switched capacitor band-pass filter and a reconstruction filter at the output. CLOCKED COMPARATOR The comparator digitizes the output signal from the 57 kHz band-pass filter for further processing by the digital RDS/RBDS demodulator. To attain high sensitivity and to avoid phase distortion, the comparator input stage contains an automatic offset compensation. DEMODULATION
SAA6588
The demodulator provides all functions of the SAA6579 but has improved performance under weak signal conditions. The demodulator includes: * 57 kHz carrier regeneration from the two sidebands (Costas loop) * Symbol integration over one RDS clock period * Bi-phase symbol decoding * Differential decoding * Synchronization of RDS/RBDS output data with clock. The RDS/RBDS demodulator recovers and regenerates the continuously transmitted RDS/RBDS data stream out of the multiplex signal (MPX) and provides the internal signals clock (RDCL) and data (RDDA) for further processing by the RDS/RBDS decoder block. RDS/RBDS data processing The RDS/RBDS data processing of the pre-processor handles the complete processing and decoding of the continuous serial RDS/RBDS demodulator output data stream. Different data processing modes are software controllable by the external main controller via I2C-bus. Processed RDS/RBDS data blocks, decoder status information and signal quality information are also available via the I2C-bus. RDS/RBDS DECODER The RDS/RBDS decoder contains: * RDS/RBDS block detection * Error detection and correction * Synchronization * Flywheel for synchronization hold * Bit slip correction * Data processing control * RDS/RBDS data output.
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Philips Semiconductors
Product specification
RDS/RBDS pre-processor
RDS/RBDS block detection
The RDS/RBDS block detection is always active. For a received sequence of 26 data bits, a valid block and its offset are identified via syndrome calculation. During synchronization search, the syndrome is calculated with every new received data bit (bit-by-bit) for a received 26-bit sequence. If the decoder is synchronized, syndrome calculation is activated only after 26 data bits for each new block received. Under RBDS reception situation, beside the RDS block sequences with (A, B, C/C', D) offset also block sequences of 4 blocks with offset E may be received. If the decoder detects an E-block, this block is marked in the block identification number BL and is available via an I2C-bus request. In RBDS processing mode the block is signed as valid E-block and in RDS processing mode, where only RDS blocks are expected, signed as invalid E-block (see Table 13). This information can be used by the main controller to detect E-block sequences and identify RDS or RBDS transmitter stations.
SAA6588
Synchronization
The decoder is synchronized if two successive valid blocks in a valid sequence are detected by the block detection. For detection of the second block of this sequence, error correction is also enabled depending on the pre-selected correction mode (see Table 4). Only valid (correctable) blocks are accepted for synchronization (see also Section "Error detection and correction"). If synchronization is found, the synchronization status flag (SYNC) is set and available via an I2C-bus request. The synchronization is held until the flywheel (for synchronization hold) detects a loss of synchronization (see Section "Flywheel for synchronization hold") or an external restart of synchronization is performed (see Section "Data processing control").
Flywheel for synchronization hold
For a fast detection of loss of synchronization the internal flywheel counter checks the number of uncorrectable blocks (error blocks). Error blocks increment and valid blocks decrement the block error counter. The flywheel counter is only active if the decoder is synchronized. The synchronization is held until the flywheel counter detects an error block overflow (loss of synchronization). The maximum value for the error block counter is adjustable via the I2C-bus in a range of 0 to 63 (see Table 6). The value 32 is set after reset and the values 0 and 63 have a special function. * If the value 0 is programmed then no flywheel is active * If the value 63 is programmed then the flywheel is endless and no new start of synchronization is effected automatically (synchronization hold).
Error detection and correction
The RDS/RBDS error detection and correction recognizes and corrects potential transmission errors within a received block via parity-check in consideration of the offset word of the expected block. Burst errors with a maximum length of 5 bits are corrected with this method. After synchronization has been found the error correction is always active, but cannot be carried out in every reception situation. During synchronization search, the error correction is disabled for detection of the first block and is enabled for processing of the second block depending on the pre-selected error correction mode for synchronization (mode SYNCA to SYNCC, see Table 4). The processed block data and the status of error correction are available for data request via the I2C-bus for the last two blocks. Processed blocks are characterized as uncorrectable under the following conditions: * During synchronization search, if the burst error is higher than allowed by the pre-selected correction mode. * After synchronization has been found, if the burst error is higher than 5 bits or if errors are detected but error correction is not possible. 2002 Jan 14 7
Bit slip correction
During poor reception situation phase shifts of one bit to the left or right (1 bit slip) between the RDS/RBDS clock and data may occur, depending on the lock conditions of the demodulators clock regeneration. If the decoder is synchronized and detects a bit slip, the synchronization is corrected by +1 or -1 bit via block detection on the respectively shifted expected new block.
Philips Semiconductors
Product specification
RDS/RBDS pre-processor
Data processing control
The pre-processor provides different operating modes selectable via the external I2C-bus. The data processing control performs the pre-selected operating modes and controls the requested output of the RDS/RBDS information. Restart of synchronization mode: The `restart synchronization' (NWSY) control mode immediately terminates the actual synchronization and restarts a new synchronization search procedure. The NWSY flag is automatically reset after the restart of synchronization by the decoder. This mode is required for a fast new synchronization on the RDS/RBDS data from a new transmitter station if the tuning frequency is changed by the radio set. Restart of synchronization search is furthermore automatically carried out if the internal flywheel signals a loss of synchronization (see Section "Flywheel for synchronization hold"). Error correction control mode for synchronization: For error correction and identification of valid blocks during synchronization search, three different modes are selectable. (SYM1, SYM0, see Table 4). RBDS processing mode: The pre-processor is suitable for receivers intended for the European (RDS) as well as for the USA (RBDS) standard. If RBDS mode is selected via the I2C-bus, the block detection and the error detection and correction are adjusted to RBDS data processing. Data available control mode: The pre-processor provides three different RDS/RBDS data output processing modes selectable via the `data available' control mode: (see also Section "RDS/RBDS data output" and Table 5). Standard processing mode: if the decoder is synchronized and a new block is received (every 26 bits), the actual RDS/RBDS information of the last two blocks is available with every new received block. Fast PI search mode: during synchronization search and if a new A-block is received, the actual RDS/RBDS information of this or the last two A-blocks respectively is available with every new received A-block. If the decoder is synchronized, the standard processing mode is valid.
SAA6588
Reduced data request processing mode: if the decoder is synchronized and two new blocks are received (every 52 bits), the actual RDS/RBDS information of the last two blocks is available with every two new received blocks. The RDS/RBDS pre-processor provides data output of the block identification, the RDS/RBDS information words and error detection and correction status of the last two blocks as well as signal quality indication and general decoder status information. In addition, the decoder controls also the data request from the external main controller. The pre-processor activates the `data overflow' status flag DOFL (see Section "Programming"), if the decoder is synchronized and a new RDS/RBDS block is received before the previously processed block was completely transmitted via I2C-bus. After detection of data overflow the interface registers are not updated until reset of the data overflow flag by reading via the I2C-bus.
RDS/RBDS data output
The decoded RDS/RBDS block information and the current pre-processor status is available via the I2C-bus. For synchronization of data request between main controller and pre-processor the additional data available output signal is used. If the decoder has processed new information for the main controller the data available signal (DAVN) is activated (LOW) under the following conditions (see also Table 5): * During synchronization search in DAVB mode if a valid A-block has been detected. This mode can be used for fast search tuning (detection and comparison of the PI code contained in the A-block). * During synchronization search in any DAV mode, if two blocks in correct sequence have been detected (synchronization criterion). * If the pre-processor is synchronized and in mode DAVA and DAVB a new block has been processed. This mode is the standard data processing mode, if the decoder is synchronized. * If the pre-processor is synchronized and in DAVC mode two new blocks have been processed. * If the pre-processor is synchronized and in any DAV mode loss of synchronization is detected (flywheel counter overflow and resulting restart of synchronization). * In any DAV mode, if a reset condition caused by power-on or voltage-drop is detected.
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Philips Semiconductors
Product specification
RDS/RBDS pre-processor
The processed RDS/RBDS data are available for I2C-bus request for at least 20 ms after the DAVN signal was activated. The DAVN signal is always automatically deactivated (HIGH) after 10 ms or almost after the main controller has read the RDS/RBDS data via I2C-bus (see Fig.4). The decoder ignores new processed RDS/RBDS blocks if the DAVN signal is active or if data overflow occurs (see Section "Data processing control"). Multi-path detector The multi-path detector takes its information from the unweighted level signal of the FM IF amplifier, input LVIN (see Fig.1). The part of frequency components around 21 kHz is selected by a band-pass filter and rectified by a full-wave rectifier. The capacitor at pin MRO is the charge capacitor. In combination with internal current sources the time constants of the rectifier are defined. The analogous output voltage of the multi-path rectifier is buffered and available via pin MPTH. Signal quality detector The signal quality detector takes its information from the multiplex signal. Disturbances caused by adjacent-channel reception, noise, or multi-path, generate high frequency components (noise) on the multiplex signal besides the audible distortion. The signal quality measurement is provided for fast testing alternative frequencies as well as for the tuned frequency. It is a short start/stop procedure. The measuring time is limited to 850 s. To attain an average value over a longer time, multiple measurements are possible with integration by software processing. The noise is detected from the frequency spectrum above 90 kHz. The noise voltage is selected by a 4th order high-pass filter. A full-wave rectifier, controlled by this noise voltage, charges an initially discharged capacitor (on chip). The time is measured until the voltage across the capacitor has reached a defined threshold value. Then that time equivalent value is stored. The resolution of the signal quality measurement is 4 bits (16 steps). For operating the noise detector two modes are provided, the triggered mode and the continuous mode. The mode is defined by the bit SQCM (Signal Quality Continuous Measurement) as described in Section "Programming".
SAA6588
The triggered mode is provided for a fast signal quality test of e.g. an alternative frequency. After the alternative frequency has been tuned, the signal quality detector has to be started (triggered) by transmitting the bits SQCM = 0 and TSQD = 1 via the I2C-bus (see Fig.5). This causes a single shot measurement immediately after the acknowledgement of this byte. The bit TSQD is internally reset during the measurement (TSQD = 0). The result of the measurement is stored and is available for reading out, as long as no new measurement is started again e.g. after tuning back to the previous frequency. The continuous mode minimizes the required I2C-bus activities for multiple measurements. After transmission of SQCM = 1 and TSQD = 1, the signal quality detector starts a new measurement as described above. But every time after finishing one measuring procedure the result is stored (overwrites the previous value within the I2C-bus buffer SQI3 to SQI0) and a new measurement starts automatically. If at any time the pre-processor is read out by his master, the last measured value will be transmitted. After transmitting the control information SQCM = 0 and TSQD = 0, the measurement activity will be stopped. A previously started but not yet finished measurement will be completed and this last result will also be available. The control bit combination SQCM = 1 and TSQD = 0 must not be used. It is reserved for later applications. At a maximum time of 850 s after triggering or automatic restart of the signal quality detector, the result of the measurement (signal quality indication) is available and represented by the four bits SQI3 to SQI0, in a value range of 0 to 15 and is available via the I2C-bus (see Section "Programming"). The result 0 characterizes no or less noise/distortion and 15 high noise/distortion. Tolerances of the signal quality detector as well as characteristics and tolerances of the FM IF amplifier can be compensated by adjusting the sensitivity of the signal quality detector with the control bits SQS0 to SQS4. The sensitivity can be adjusted over a range of 18.6 dB (-9.0 to +9.6 dB) in steps of 0.6 dB as given in Table 10. Pause detector The pause detector watches the audio modulation for pauses or very low levels. This function can be used for performing inaudible RDS AF-tests if the radio is in FM mode as well as for Automatic Music Search (AMS) if the radio is in cassette mode.
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Philips Semiconductors
Product specification
RDS/RBDS pre-processor
The input of the pause detector (AFIN) is low-ohmic and must be current driven (negative input of an operational amplifier). This has the following advantages: * One (MPX) as well as two (left and right) AF channel application is possible and requires only one pin * Unwanted crosstalk is avoided if two AF channel application is chosen * Matching the input sensitivity is possible by external resistors. For combined application (RDS and AMS) variations of the switching threshold level as well as the minimum time for pause detection are possible via I2C-bus control. The level can be adjusted in four steps of 4 dB by the control bits PL0 and PL1, see Table 8 (for 1 channel: R = 5 k; for 2 channels: R = 10 k). The corresponding values of FM deviation are calculated for stereo decoders with an output voltage of 270 mV at 22.5 kHz deviation. The minimum time for detecting a pause can be adjusted by the control bits SOSC, PTF0 and PTF1; see Table 9. The minimum time for detecting `no pause' is fixed to 5 ms to avoid interruptions of a pause by a short pulse. The output signal of the pause detector is a digital switching signal (active LOW). It is directly available via the output pin PSWN. A detected pause may initiate an AF search if required (FM mode). Oscillator and clock For good performance of the band-pass and demodulator stages, the pre-processor requires a crystal oscillator with a frequency of n x 4.332 MHz. The pre-processor can be operated with one of four different oscillator frequencies (n = 1 to 4). The 17.328 MHz frequency (n = 4) is also UART interface compatible for 8051 based microcontrollers with a 9600 baud rate (frequency error = 4.5%), so that a radio set with microcontroller can run in this case with one crystal only. The pre-processor oscillator can drive the microcontroller or vice versa. According to the used oscillator frequency, the mode control bits PTF1, PTF0 and SOSC have to be set via the I2C-bus after every reset, see Section "Programming" The clock generator circuitry generates hereof the internally used 4.332 MHz system clock and further derived timing signals. Power supply and reset
SAA6588
The pre-processor has separate power supply inputs for the digital and analog parts of the device. For the analog functions an additional reference voltage (12VDDA) is internally generated and available via the output pin Vref. The I2C-bus interface requires a defined reset condition. The pre-processor generates a reset signal: * After the supply voltage VDDD is switched on * At a supply voltage drop * If the oscillator frequency is lower than 400 Hz. This internal reset initializes the I2C-bus interface registers as well as the I2C-bus slave control and releases the data line SDA (SDA = HIGH) for input of control mode settings from the main controller. If the decoder detects a reset condition, the status information `reset detected' (RSTD) is set and available via I2C-bus request. The RSTD flag is deactivated after the decoder status register was read by the I2C-bus. This status information is important to signal the main controller about a voltage drop in the pre-processor IC. By default, the bits in the write registers (except bit SOSC) are set to the values in Table 11. If these values are the required values, no further initialization is necessary. Programming I2C-BUS SLAVE TRANSCEIVER For communication with the external main controller (master transceiver) the standard I2C-bus is used. The pre-processors I2C-bus interface acts as a slave transceiver with fast mode option, that allows a transfer bit rate up to 400 kbits/s but is also capable of operating at lower rates (100 kbits/s). The I2C-bus interface is connected to the external I2C-bus via the serial clock line SCL and the serial data line SDA. The clock line is supplied by the master and is only input for the slave transceiver. The data line is a serial 8-bit oriented bidirectional data transfer line, and acts as input for control mode settings from the main controller to the pre-processor, as output for requested RDS/RBDS data from the pre-processor to the main controller and acknowledge between pre-processor and main controller.
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Philips Semiconductors
Product specification
RDS/RBDS pre-processor
The transfer of requested data to the main controller is synchronized via the additional data available output signal DAVN to avoid loss of RDS/RBDS data. The DAVN signal is activated if the pre-processor has provided new data information for the main controller (see Section "RDS/RBDS data output") and can be used for the polling mode as well as for the interrupt mode of the main microcontroller. I2C-BUS INTERFACE REGISTERS The I2C-bus interface is connected to other blocks of the pre-processor via internal registers (byte oriented). Those can either be written by the pre-processor control and read by the main controller I2C-bus or vice versa. The device provides 3 input control registers to which may be written via the I2C-bus and 7 output registers which may be read via the I2C-bus. The decoder control updates the output registers after the detection of a new RDS/RBDS information block and reads the new mode control settings of the input control registers. Both operations may occur in the same time slot, provided that the read operation is complete before a new RDS/RBDS data bit is processed by the demodulator. For the corresponding access the registers are addressed by two separate register pointers, write-enable and read-enable signals, which are activated either via the decoder control or via the I2C-bus interface control. During a read or write transmission from the I2C-bus the read/write pointer selects the register of the first byte for transmission and is auto-incremented by the I2C-bus control for the transfer of subsequent bytes. During a write transmission after reception of the device slave address and write bit, the mode control settings for the pre-processor have to be send in the protocol sequence as shown in Table 1 and Fig.5. During a read cycle after reception of the device slave address and read bit the requested RDS/RBDS data has to be received in the protocol sequence as given in Table 2 and Fig.7. Table 2 DATA Byte 0R Byte 1R Byte 2R Byte 3R Byte 4R Byte 5R Byte 6R Table 1 DATA Byte 0W Byte 1W Byte 2W Input control registers
SAA6588
FUNCTION initialization and mode control setting; see Table 3 pause level and flywheel setting; see Table 6 pause time/oscillator frequency and quality detector sensitivity setting; see Table 7 Output registers FUNCTION decoder and data status information; see Table 12 last processed block (HIGH byte); see Table 15 last processed block (LOW byte); see Table 15 previously processed block (HIGH byte); see Table 15 previously processed block (LOW byte); see Table 15 error status information; see Table 15 signal quality indication; see Table 15
WRITE TRANSMISSION FORMAT Table 3 Description of initialization and mode control byte (byte 0W) FUNCTION 1: signal quality continuous measurement 6 TSQD 0: no determination of signal quality 1: trigger of signal quality detector measurement 5 4 3 2 1 0 NWSY 0: normal processing mode 1: restart of synchronization SYM1 selection of error correction mode for SYM0 synchronization search; see Table 4 RBDS 0: RDS processing mode 1: RBDS processing mode DAC1 selection of data output protocol and DAC0 indirectly control of data available output signal (DAVN); see Table 5
BIT NAME 7
SQCM 0: triggered signal quality measurement
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Philips Semiconductors
Product specification
RDS/RBDS pre-processor
Table 4 SYM1 0 0 1 1 Selection of error correction mode for synchronization search SYM0 0 1 0 1 MODE SYNCA SYNCB SYNCC SYNCD no error correction DESCRIPTION
SAA6588
error correction of a burst error maximum 2 bits error correction of a burst error maximum 5 bits no error correction; no E-E block sequence allowed (for RBDS mode, E-A or D-E block sequences are still allowed)
Table 5 DAC1 0
Selection of data output protocol and DAVN signal DAC0 0 MODE DAVA FUNCTION standard processing mode DESCRIPTION RDS standard output mode; synchronization search: DAVN = HIGH; synchronized: block information available and DAVN active after detection of a new block (every 26 bits) synchronization search: for fast PI search, block information available and DAVN active only if a correct A-block is detected; synchronized: same as standard DAVA mode synchronization search: DAVN inactive = HIGH; synchronized: block information available and DAVN active only after detection of two new blocks (every 52 bits) -
0
1
DAVB
fast PI search mode reduced data request processing mode -
1
0
DAVC
1 Table 6 BIT 7 6 5 to 0 Table 7 BIT 7 6 5 4 to 0 Table 8
1
-
Description of pause level and flywheel setting bytes (byte1W) NAME PL1 PL0 FEB5 to FEB0 maximum number of error blocks for synchronization hold flywheel (0 to 63) FUNCTION level sensitivity for pause detection; see Table 8
Description of pause time/oscillator frequency and quality detector sensitivity setting (byte 2W) NAME PTF1 PTF0 SOSC SQS4 to SQS0 FUNCTION time criteria for pause (20 to 160 ms); see Table 9 oscillator frequency: n x 4.332 MHz (n = 1 to 4); see Table 9 0: set pause time criteria via PFT1 and PFT0 1: select oscillator frequency via PFT1 and PFT0 adjustment of signal quality detector sensitivity (-9 to +9.6 dB); see Table 10
Control bits PL0 and PL1 PL1 0 0 1 1 PL0 0 1 0 1 PAUSE LEVEL (mV RMS) 11 17 27 43 BELOW DOLBY LEVEL (dB) 30.2 26.2 22.2 18.2 FM DEVIATION (kHz) 1.0 1.6 2.5 4.0
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Philips Semiconductors
Product specification
RDS/RBDS pre-processor
Table 9 Control bits SOSC, PTF0 and PTF1 SOSC = 0 SOSC 0 0 0 0 PTF1 0 0 1 1 PTF0 0 1 0 1 MINIMUM TIME (ms) 20.2 40.4 80.8 161.7
SAA6588
SOSC = 1 OSCILLATOR FREQUENCY (MHz) 4.332 (n = 1) 8.664 (n = 2) 12.996 (n = 3) 17.328 (n = 4)
Table 10 Control bits SQS0 to SQS4 SQS SQS4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 SQS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SQS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 SQS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 SQS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 HEX 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F CORRECTION (dB) -9.0 -8.4 -7.8 -7.2 -6.6 -6.0 -5.4 -4.8 -4.2 -3.6 -3.0 -2.4 -1.8 -1.2 -0.6 0 +0.6 +1.2 +1.8 +2.4 +3.0 +3.6 +4.2 +4.8 +5.4 +6.0 +6.6 +7.2 +7.8 +8.4 +9.0 +9.6
2002 Jan 14
13
Philips Semiconductors
Product specification
RDS/RBDS pre-processor
Table 11 Default values of the write register bits after reset BIT SQCM TSQD NWSY VALUE 0 0 1 COMMENTS triggered signal quality measurement no determination of signal quality restart of synchronization no error correction during synchronization RDS processing mode pause level 12 mV DAVA mode RDS standard output mode oscillator frequency = 4.332 MHz (SOSC = 1); pause time = 20.2 ms (SOSC = 0) gain = 0 dB Table 14 Processed error correction ELB1/ EPB1 0 0 1 1 ELB0/ EPB0 0 1 0 1 MODE ERDA ERDB ERDC ERDD
SAA6588
Table 13 Block identification number (last detected block) BL2/ BP2 0 0 0 0 1 1 1 1 BL1/ BP1 0 0 1 1 0 0 1 1 BL0/ BP0 0 1 0 1 0 1 0 1 BLOCK IDENTIFICATION block A block B block C block D block C' block E (RBDS mode) invalid block E (RDS mode) invalid block
SYM1 and SYM0 00 RBDS PL1 and PL0 DAC1 and DAC0 FEB5 to FEB0 PTF1 and PTF0 0 00 00
100000 flywheel = 32 decimal 00
DESCRIPTION no errors detected burst error of maximum 2 bits corrected burst error of maximum 5 bits corrected uncorrectable block
SQS4 to SQS0
01111
READ TRANSMISSION FORMAT Table 12 Description of decoder and data status information byte (byte 0R) BYTE 0R BIT NAME FUNCTION
Table 15 Bytes 1R to 6R BYTE 1R 2R 3R 4R 5R BIT 7 to 0 7 to 0 7 to 0 7 to 0 7 to 2 1 0 6R 7 to 5 NAME M15 to M08 M07 to M00 PM15 to PM08 PM07 to PM00 BEC5 to BEC0 EPB1 EPB0 BP2 to BP0 - SQI3 to SQI0 FUNCTION HIGH byte of last processed block LOW byte of last processed block HIGH byte of previously processed block LOW byte of previously processed block number of counted block errors (0 to 63) error status of previously processed block; see Table 14 block identification number of previous processed block; see Table 13 not used (undefined) signal quality indication (0 to 15)
7 to 5 BL2 to BL0 block identification number of last processed block; see Table 13 4 3 2 1 0 SYNC DOFL RSTD ELB1 ELB0 0: not synchronized 1: synchronized 0: no data overflow 1: data overflow detected 0: no reset detected 1: reset detected error status of last processed block; see Table 14
4 3 to 0
2002 Jan 14
14
Philips Semiconductors
Product specification
RDS/RBDS pre-processor
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134). SYMBOL VDD Vn Vi(MPX)(p-p) Ii PARAMETER supply voltage voltage at pins 1 to 5, 8 to 13, and 16 to 20 with respect to pins 6 and 15 input voltage at pin MPX (peak-to-peak value) input current pins 1 to 5, 8, 10 to 13 and 16 to 20 pin 9 Ilu(prot) latch-up protection current in pulsed mode Tamb = -40 to +85 C with voltage limiting -2 to +10 V Tamb = 25 C with voltage limiting -2 to +12 V Tamb = -40 to +85 C without voltage limiting Tamb Tstg Ves operating ambient temperature storage temperature electrostatic handling note 2 note 3 Notes 1. Without latching in the entire temperature range. -10 -20 -100 -200 -10 -40 -65 -4000 -250 +10 +20 +100 +200 +10 +85 +150 +4000 +250 note 1 CONDITIONS 0 -0.5 - MIN. 6.5
SAA6588
MAX.
UNIT V
VDD + 0.5 6.5 V 6 V
mA mA mA mA mA C C V V
2. Human body model (equivalent to discharging a 100 pF capacitor through a 1.5 k series resistor). Except pin 17: -4000 V minimum and +2500 V maximum. 3. Machine model (equivalent to discharging a 200 pF capacitor through a 0 series resistor and 0.75 H inductance). THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient SAA6588T (SOT163-1) SAA6588 (SOT146-1) CONDITIONS in free air 85 62 K/W K/W VALUE UNIT
2002 Jan 14
15
Philips Semiconductors
Product specification
RDS/RBDS pre-processor
CHARACTERISTICS DIGITAL PART VDDA = VDDD = 5 V; Tamb = 25 C; unless otherwise specified. SYMBOL Supply VDDD IDDD Ptot Inputs VIL1 VIL2 VIH1 VIH2 ILI Ii(pu) Outputs VOL1 VOL2 VOH LOW-level output voltage at pins DAVN, PSWN and OSCO LOW-level output voltage at pin SDA HIGH-level output voltage at pins DAVN, PSWN and OSCO IOL = 2 mA IOL1 = 4.0 mA IOL2 = 6.0 mA IOH = -2 mA - - - 4.0 - - - - 0.4 0.4 0.6 - LOW-level input voltage at pins TCON, OSCI and MAD LOW-level input voltage at pins SCL and SDA HIGH-level input voltage at pins TCON, OSCI and MAD HIGH-level input voltage at pins SCL and SDA input leakage current at pins TCON, SCL and SDA input pull-up current at pin MAD VDDD = 4.5 to 5.5 V VMAD = 0 to VDDD VMAD = VIL1 VMAD = 3.5 V VDDD = 4.5 to 5.0 V VDDD = 5.0 to 5.5 V - -0.5 -0.5 - - - digital supply voltage digital supply current total power dissipation 4.5 - - 5.0 6.0 70 5.5 - - PARAMETER CONDITIONS MIN. TYP.
SAA6588
MAX.
UNIT
V mA mW
0.3VDDD +1.5 +0.3VDDD -
V V V V
0.7VDDD - 3.0 - -30 - - - -20 -20
VDDD + 0.5 V 10 - -10 A A A V V V V
Crystal parameters fi(xtal) crystal input frequency n=1 n=2 n=3 n=4 fosc fosc(T) CL Rxtal adjustment tolerance of oscillator frequency temperature drift of oscillator frequency load capacitance crystal resonance resistance fosc 12.996 MHz fosc = 17.328 MHz Tamb = -40 to +85 C - - - - - - - - - 4.332 8.664 12.996 17.328 - - 30 - - - - - - 30 30 - 120 60 MHz MHz MHz MHz ppm ppm pF
2002 Jan 14
16
Philips Semiconductors
Product specification
RDS/RBDS pre-processor
CHARACTERISTICS ANALOG PART VDDA = VDDD = 5 V; Tamb = 25 C; measurements taken in Fig.1; unless otherwise specified. SYMBOL Supply VDDA analog supply voltage 4.5 - - VDDA = 5 V 2.25 - f = 1.2 kHz RDS signal; f = 3.2 kHz spurious signal f = 57 2 kHz f < 50 kHz f < 15 kHz f > 70 kHz Ri(MPX) fc B-3dB GMPX sb input resistance f = 0 to 100 kHz Tamb = -40 to +85 C f = 57 kHz f = 7 kHz f < 45 kHz f < 20 kHz f > 70 kHz Ro(SCOUT) Vi(min)(rms) Ri Zi(LVIN) Vi(LVIN) fc(MPD) output resistance at pin SCOUT f = 57 kHz Comparator input (pin CIN) minimum input level (RMS value) input resistance f = 57 kHz - 70 1 110 57 kHz band-pass filter centre frequency -3 dB bandwidth signal gain stop band attenuation 56.5 2.5 17 31 40 50 40 - 57.0 3.0 20 - - - - 30 1 200 1.4 2.8 3.5 33 5.0 0 14.0 2.5 25 - - - - - - PARAMETER CONDITIONS MIN. TYP.
SAA6588
MAX.
UNIT
5.5 0.5 - 2.75 - - - - - - - 57.5 3.5 23 - - - - 60
V V mA V k
VDDA - VDDD voltage difference between analog and digital supply IDD(tot) Vref Zo(Vref) Vi(MPX)(rms) Vi(max)(p-p) total supply current reference voltage output impedance at pin Vref RDS amplitude (RMS value) maximum input signal capability (peak-to-peak value)
MPX input (signal before the capacitor on pin MPX) mV mV V V V k
kHz kHz dB dB dB dB dB mV k
10 150
Multi-path detector (pins LVIN, MPTH and MRO) input impedance at pin LVIN input voltage at pin LVIN centre frequency of the multi-path detector band-pass filter bandwidth of the multi-path detector band-pass filter stop band attenuation attack time of the rectifier f = 11 kHz f = 31 kHz tatt(MRO) 2002 Jan 14 C6 = 100 nF; R4 = 470 k 17 f = 21 kHz 24 1.0 20 30 2.5 21 36 4.0 22 k V kHz
BMPD sb
3.6 16 12 -
4.0 - - 6.4
4.4 - - -
kHz dB dB ms
Philips Semiconductors
Product specification
RDS/RBDS pre-processor
SAA6588
SYMBOL tdec(MRO) Gv(MPTH)
PARAMETER decay time of the rectifier rectifier voltage gain; G v(MPTH) V MPTH(DC) = 20 log ------------------------V LVIN(rms)
CONDITIONS C6 = 100 nF; R4 = 470 k VLVIN(rms) = 0.1 V; fLVIN = 21 kHz
MIN. - -
TYP. 50 20
MAX. - -
UNIT ms dB
Zo(MPTH) Vo(MPTH) ZL(MPTH) CL(MPTH) fco PBRR sb VSTEP2-3(rms)
output impedance at pin MPTH output voltage swing at pin MPTH load impedance at pin MPTH load capacitance at pin MPTH with respect to ground with respect to ground
150 0.5 5 - 85 - f = 40 kHz 30 sensitivity = 0 dB - (SQS = 01111; see Table 10); f = 100 kHz 0.4 15.6 after acknowledgement of the I2C-bus transceiver -
200 - - - 90 - - 85
250 3.5 - 20
V k pF
Signal quality detector (pin MPX) cut-off frequency pass-band ripple rejection stop band attenuation input voltage (RMS value) for transition of signal quality indication between step 2 and 3 (SQI = 0010 and 0011) step size for signal quality input gain control range for signal quality input gain measuring time 95 1 - - kHz dB dB mV
GSQ CRGSQ tSQD
0.6 18.6 -
0.8 21.6 850
dB dB s
Pause detector (pins AFIN and PSWN) Zi(AFIN) VI(AFIN) Ith(rms) THpause(step) THpause(R) Ii(offset) tPON(min) input impedance DC input voltage AC input current for threshold (RMS value) step size for pause threshold control range for pause threshold input offset current minimum time for pause PT1 = 0; PT0 = 0 PT1 = 0; PT0 = 1 PT1 = 1; PT0 = 0 PT1 = 1; PT0 = 1 tPOFF(min) t minimum time for no pause time error (all values) f = 10 kHz unloaded PL1 = 1; PL0 = 1 - - 3.1 3 10 - - - - - - - - Vref 4.4 4 12 - 20.2 40.4 80.8 161.7 5 - 10 - 6.2 5 14 0.4 - - - - - 1.0 V A dB dB A ms ms ms ms ms ms
2002 Jan 14
18
Philips Semiconductors
Product specification
RDS/RBDS pre-processor
I2C-BUS PROTOCOL I2C-bus format In communication with the pre-processor two basic types of I2C-bus protocols are allowed (see Tables 16 and 17). Every transmission begins with a START condition `S' followed by the 7-bit slave address and the R/W mode bit, all generated by the external master. The 6 higher bits of the pre-processors slave address are fixed to 001000. The least significant bit of the slave address can be set via the external input pin MAD to enable a variation if the slave address is already occupied by another device of the radio set. Data is transferred with the most significant bit (MSB) first. Table 16 Transmitting to the pre-processor (write transfer) S(1) Notes 1. S = START condition. 2. Slave address (depends on level at pin MAD) = 0010000 or 0010001. 3. W = write mode. 4. A = acknowledge bit (SDA = LOW). 5. Subsequently data bytes 0W, 1W and 2W. 6. P = STOP condition. Table 17 Receiving from the pre-processor (read transfer) S(1) Notes 1. S = START condition. 2. Slave address (depends on level at pin MAD) = 0010000 or 0010001. 3. R = read mode. SLAVE ADDRESS(2) R(3) A(4) DATA(5) A(4) DATA(5) A(6) SLAVE ADDRESS(2) W(3) A(4) DATA(5) A(4) DATA(5) A(4) DATA(5)
SAA6588
Each transmitted byte is followed by an acknowledge bit `A' (SDA = LOW). Every transmission is completed with a STOP condition `P' generated by the master. During read or write transfer the master can abridge the data transfer by generation of a STOP condition. In case of transmission errors during a write cycle, the pre-processor can indirectly stop the transfer by generating no acknowledge (SDA = HIGH) hereafter the master can send the STOP condition.
A(4)
P(6)
P(7)
4. A = acknowledge bit (SDA = LOW). Six DATA-acknowledge sequences must occur before the DATA-not acknowledge sequence. 5. Subsequently data bytes 0R to 6R. 6. A = no acknowledge (SDA = HIGH). 7. P = STOP condition.
2002 Jan 14
19
Philips Semiconductors
Product specification
RDS/RBDS pre-processor
Timing data
SAA6588
handbook, full pagewidth
tDAVL DAVN tDVL tTDAV tDV
DATA
MGK540
a. No I2C-bus request during DAVN LOW-time (decoder is synchronized).
handbook, full pagewidth
pre-processor addressed I2C-BUS
tDAVL DAVN tDVL tTDAV tDV
DATA
MGK541
b. DAVN LOW-time shortened by data-request via I2C-bus (decoder is synchronized).
Fig.4 Data available signal (DAVN).
Table 18 Data available signal (DAVN) SYMBOL tDVL tTDAV tDV tDAVL PARAMETER data valid to DAVN LOW data valid period data valid data available signal is LOW 2.0 21.9 21.9 10.1(1) depends on data request via I2C-bus(2) Notes 1. See Fig.4a. 2. See Fig.4b. 2002 Jan 14 20 TYP. s ms ms ms ms UNIT
Philips Semiconductors
Product specification
RDS/RBDS pre-processor
PROGRAMMING AND I2C-BUS SUMMARY
SAA6588
handbook, full pagewidth
START condition from master
slave address + write-bit from master
acknowledgement from slave
S
0
0
1
0
0
0
MAD
0
A
byte 0W from master
acknowledgement from slave
SQCM TSQD NWSY SYM1 SYM0 RBDS DAC1 DAC0
A
byte 1W from master
acknowledgement from slave
PL1
PL0
FEB5 FEB4 FEB3 FEB2 FEB1 FEB0
A
byte 2W from master
acknowledgement from slave
PTF1 PTF0 SOSC SQS4 SQS3 SQS2 SQS1 SQS0
A
P
MGK538
STOP condition from master
Fig.5 RDS pre-processor control commands: mode control and preset settings for the pre-processor.
handbook, full pagewidth
START condition from master
slave address + write-bit from master
acknowledgement from slave
S
0
0
1
0
0
0
MAD
0
A
byte 0W from master
acknowledgement from slave
SQCM TSQD
1
SYM1 SYM0 RBDS DAC1 DAC0
A
P
MGK539
STOP condition from master
Fig.6
RDS pre-processor control commands: abridged protocol, for example for immediate restart synchronization.
2002 Jan 14
21
Philips Semiconductors
Product specification
RDS/RBDS pre-processor
SAA6588
handbook, full pagewidth START condition
from master
slave address + read-bit from master
S
0
0
1
0
0
0
MAD
1
A
byte 0R from device
BL2
BL1
BL0
SYNC DOFL RSTD ELB1 ELB0
A
higher byte of last processed block from device
M15
M14
M13
M12
M11
M10
M09
M08
A
lower byte of last processed block from device
M07
M06
M05
M04
M03
M02
M01
M00
A
higher byte of previous processed block from device
PM15 PM14 PM13 PM12 PM11 PM10 PM09 PM08
A
lower byte of previous processed block from device
PM07 PM06 PM05 PM04 PM03 PM02 PM01 PM00
A
byte 5R from device
BEC5 BEC4 BEC3 BEC2 BEC1 BEC0 EPB1 EPB0
A
byte 6R from device not used
not acknowledged from master
BP2
BP1
BP0
SQI3
SQI2
SQI1
SQI0
A
P
MGK537
STOP condition from master
Fig.7 Data output protocol (RDS data output).
2002 Jan 14
22
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2002 Jan 14
S_DAVN
(1)
APPLICATION DIAGRAM
Philips Semiconductors
RDS/RBDS pre-processor
(1)
C18 1 nF
C1 1.5 nF
(1) (3)
R4 +5 V C2 220 pF C6 47 F R3 10 470
(1)
S_SDA
L1
(1) (2)
(1) (3)
R5 270
(1) (3)
(1)
R7 470
S_SCL
(1) (3)
C3 220 pF
(1)
PSWN
11
10
SCL
R6 270
S_PSWN C4 1.5 nF +5 V R1 10 k C7 470 nF R2 10 k C8 C9 470 nF 100 nF
MAD
12
9
SDA DAVN
AFIN VDDA VSSA MPX C11 2.2 F SCOUT C12 560 pF Vref
13
8 VDDD VSSD OSCI R8 1 k HC49/U Q1 (4) C16 82 pF R11 10 (1) C14 100 nF 5
GND
14
7
GND
(1)
C51 470 pF
15
6
23
AF1 AF2 MUX LVL S_MPTH (1) (2) (3) (4)
C10 330 pF
SAA6588
16
17
4
OSCO
C15 47 pF
18
3
TCON
CIN
19
2
MPTH
C13 2.2 nF R9 1 k
(1)
LVIN
20
1
MRO C17 100 nF R10 470 k
MGK536
Product specification
Components for suppression of electromagnetic emission (EME). L1 = type EMIFIL, part number BLM21A102S (MURATA) or equivalent. Values for standard mode I2C-bus. Necessary pull-up resistors of 1.8 k are part of the I2C-bus interface. Q1: 4.332 MHz, 8.664 MHz, 12.996 MHz or 17.328 MHz.
SAA6588
Fig.8 Application diagram.
Philips Semiconductors
Product specification
RDS/RBDS pre-processor
PACKAGE OUTLINES DIP20: plastic dual in-line package; 20 leads (300 mil)
SAA6588
SOT146-1
D seating plane
ME
A2
A
L
A1
c Z e b1 b 20 11 MH wM (e 1)
pin 1 index E
1
10
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 4.2 0.17 A1 min. 0.51 0.020 A2 max. 3.2 0.13 b 1.73 1.30 0.068 0.051 b1 0.53 0.38 0.021 0.015 c 0.36 0.23 0.014 0.009 D
(1)
E
(1)
e 2.54 0.10
e1 7.62 0.30
L 3.60 3.05 0.14 0.12
ME 8.25 7.80 0.32 0.31
MH 10.0 8.3 0.39 0.33
w 0.254 0.01
Z (1) max. 2.0 0.078
26.92 26.54 1.060 1.045
6.40 6.22 0.25 0.24
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT146-1 REFERENCES IEC JEDEC MS-001 EIAJ SC-603 EUROPEAN PROJECTION
ISSUE DATE 95-05-24 99-12-27
2002 Jan 14
24
Philips Semiconductors
Product specification
RDS/RBDS pre-processor
SAA6588
SO20: plastic small outline package; 20 leads; body width 7.5 mm
SOT163-1
D
E
A X
c y HE vMA
Z 20 11
Q A2 A1 pin 1 index Lp L 1 e bp 10 wM detail X (A 3) A
0
5 scale
10 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 2.65 0.10 A1 0.30 0.10 A2 2.45 2.25 A3 0.25 0.01 bp 0.49 0.36 c 0.32 0.23 D (1) 13.0 12.6 0.51 0.49 E (1) 7.6 7.4 0.30 0.29 e 1.27 0.050 HE 10.65 10.00 L 1.4 Lp 1.1 0.4 Q 1.1 1.0 0.043 0.039 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z
(1)
0.9 0.4 0.035 0.016
0.012 0.096 0.004 0.089
0.019 0.013 0.014 0.009
0.419 0.043 0.055 0.394 0.016
8o 0o
Note 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. OUTLINE VERSION SOT163-1 REFERENCES IEC 075E04 JEDEC MS-013 EIAJ EUROPEAN PROJECTION
ISSUE DATE 97-05-22 99-12-27
2002 Jan 14
25
Philips Semiconductors
Product specification
RDS/RBDS pre-processor
SOLDERING Introduction This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mount components are mixed on one printed-circuit board. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. Through-hole mount packages SOLDERING BY DIPPING OR BY SOLDER WAVE The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joints for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. MANUAL SOLDERING Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds. Surface mount packages REFLOW SOLDERING Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method.
SAA6588
Typical reflow peak temperatures range from 215 to 250 C. The top-surface temperature of the packages should preferable be kept below 220 C for thick/large packages, and below 235 C for small/thin packages. WAVE SOLDERING Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. MANUAL SOLDERING Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 26
2002 Jan 14
Philips Semiconductors
Product specification
RDS/RBDS pre-processor
Suitability of IC packages for wave, reflow and dipping soldering methods
SAA6588
SOLDERING METHOD MOUNTING PACKAGE WAVE Through-hole mount DBS, DIP, HDIP, SDIP, SIL Surface mount BGA, HBGA, LFBGA, SQFP, TFBGA HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, HVQFN, SMS PLCC(4), SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO Notes 1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the "Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods". 2. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. 3. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. 4. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. 5. Wave soldering is only suitable for LQFP, QFP and TQFP packages with a pitch (e) equal to or larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. 6. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. suitable(2) not suitable not suitable(3) suitable not recommended(4)(5) not recommended(6) REFLOW(1) DIPPING - suitable suitable suitable suitable suitable suitable - - - - -
2002 Jan 14
27
Philips Semiconductors
Product specification
RDS/RBDS pre-processor
DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS
SAA6588
This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A.
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. DISCLAIMERS Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
2002 Jan 14
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Philips Semiconductors
Product specification
RDS/RBDS pre-processor
PURCHASE OF PHILIPS I2C COMPONENTS
SAA6588
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2002 Jan 14
29
Philips Semiconductors
Product specification
RDS/RBDS pre-processor
NOTES
SAA6588
2002 Jan 14
30
Philips Semiconductors
Product specification
RDS/RBDS pre-processor
NOTES
SAA6588
2002 Jan 14
31
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753503/02/pp32
Date of release: 2002
Jan 14
Document order number:
9397 750 09197

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